This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2002-029170, filed on Feb. 6, 2002, the entire contents of which are incorporated herein by reference.
1) Field of the Invention
The present invention relates to a code generation device, a semiconductor device, and a receiver device. In particular, the present invention relates to a code generation device which generates a predetermined code, a semiconductor device including a code generation device which generates a predetermined code, and a receiver device which generates a predetermined code, and decodes a received signal by using the predetermined code.
2) Description of the Related Art
In the spread spectrum communication methods, spreading modulation is performed for transmission by using a different spreading code for each communication channel. On the receiver side, reverse spreading must be performed by using the same spreading code as that used on the transmitter side. Therefore, it is necessary to detect the spreading code and establish a timing of the spreading code in initial synchronization.
As a method of initial synchronization, the three-stage initial synchronization method is known. In the three-stage initial synchronization method, chip synchronization is established in the first stage, a spreading code group is identified and a frame timing is established in the second stage, and a spreading code is identified in the third stage.
In the second and third stages, a challenge which is to be solved for improving system performance is to identify one of a plurality of types of spreading codes at the earliest possible time. In the case where a matched filter is used, a received baseband signal is stored, a correlation between the received baseband signal and a sequence of a plurality of spreading codes is detected, and detection of a spreading code and establishment of the timing of the spreading code are achieved.
A construction of a circuit of a conventional initial synchronization device using a matched filter is explained with reference to FIG. 8. The initial synchronization device in FIG. 8 comprises a code generation circuit 10, a serial-to-parallel conversion circuit 11, a shift register 12, multipliers 13-1 to 13-m, and an adder 14. The initial synchronization device generates a hierarchized orthogonal code, and calculates and outputs a correlation value between the hierarchized orthogonal code and a received baseband signal.
The code generation circuit 10 comprises a channelization-code number generation circuit 10a, a scrambling-code number generation circuit 10b, a channelization-code generation circuit 10c, a scrambling-code generation circuit 10d, and a multiplier 10e. The code generation circuit 10 generates and outputs a spreading code.
The channelization-code number generation circuit 10a is a number fixedly assigned to each user.
The scrambling-code number generation circuit 10b is a number for designating a Gold code as a scrambling code.
The channelization-code generation circuit 10c generates a hierarchized orthogonal code corresponding to the channelization-code number generation circuit 10a. 
The scrambling-code generation circuit 10d generates a Gold code corresponding to the scrambling-code number 10b. 
The multiplier 10e calculates and outputs bitwise exclusive logical sums between the hierarchized orthogonal code output from the channelization-code generation circuit 10c and the Gold code output from the scrambling-code generation circuit 10d. 
The serial-to-parallel conversion circuit 11 converts a (serial) bit signal output from the multiplier 10e, into a parallel signal, and outputs the parallel signal.
The shift register 12 receives a baseband signal, shifts the received baseband signal bit by bit, and outputs the shifted result as a parallel signal to the multipliers 13-1 to 13-m.
The multipliers 13-1 to 13-m calculate and output bitwise products of the parallel signal output from the serial-to-parallel conversion circuit 11 and the parallel signal output from the shift register 12.
The adder 14 calculates a sum of the outputs of the multipliers 13-1 to 13-m, and outputs the sum as a xe2x80x9ccorrelation output.xe2x80x9d
Next, details of the construction of the channelization-code generation circuit 10c illustrated in FIG. 8 are explained with reference to FIG. 9. As illustrated in FIG. 9, the channelization-code generation circuit 10c comprises a code-phase generation circuit 20, AND gates 21 to 29, an EXCLUSIVE-OR gate 30, and a register 31.
The code-phase generation circuit 20 generates and outputs data 0 to 511 as a code phase.
The AND gates 21 to 29 calculate and output bitwise logical products of the hierarchical-orthogonal-code number k as the channelization-code number 10a and the code phase n output from the code-phase generation circuit 20.
The EXCLUSIVE-OR gate 30 calculates and outputs an exclusive logical sum of the outputs of the AND gates 21 to 29.
The register 31 stores and outputs all bits of data (as hierarchized orthogonal codes Ck,n) output from the EXCLUSIVE-OR gate 30.
Next, the operations of the above conventional example are explained. As an example, the operations for timing synchronization are explained below.
The channelization-code generation circuit 10c receives a channelization-code number 10a which is assigned to each user, and generates a channelization code corresponding to the channelization-code number 10a. 
Thus, a plurality of bits constituting the hierarchical-orthogonal-code number k as the channelization-code number are respectively supplied to the AND gates 21 to 29 in the channelization-code generation circuit 10c. On the other hand, the code-phase generation circuit 20 successively generates the data 0 to 511 as the code phase, and a plurality of bits constituting the data of the code phase are respectively supplied to the AND gates 21 to 29. At this time, the plurality of bits of the code phase data supplied to the AND gates 21 to 29 are arranged in reverse order to the plurality of bits of the hierarchical-orthogonal-code number k supplied to the AND gates 21 to 29.
The AND gates 21 to 29 calculate and output bitwise logical products of the hierarchical-orthogonal-code number k as the channelization-code number generation circuit 10a and the code phase n output from the code-phase generation circuit 20.
The EXCLUSIVE-OR gate 30 calculates and outputs an exclusive logical sum of the outputs of the AND gates 21 to 29.
The register 31 stores bit data being output from the EXCLUSIVE-OR gate 30 and corresponding to the code phase 0 to 511, and outputs the bit data as hierarchized orthogonal codes.
On the other hand, the scrambling-code generation circuit 10d generates and outputs a Gold code as a scrambling code corresponding to the scrambling-code number generation circuit 10b. The Gold code is basically a code sequence obtained by adding two M-sequences having an identical period, and has a code length corresponding to a plurality of symbol lengths while the code length of the channelization code is the symbol length.
The multiplier 10e calculates and outputs a product of the data output from the channelization-code generation circuit 10c and the data output from the scrambling-code generation circuit 10d. As mentioned before, the bit length of the scrambling code is greater than the bit length of the channelization code. Therefore, the channelization-code generation circuit 10c repeatedly outputs identical codes, and the multiplier 10e calculates and outputs bitwise exclusive logical sums, a product of the scrambling code and the channelization code which is repeatedly output.
The serial-to-parallel conversion circuit 11 stores the serial data output from the multiplier 10e, in a register built in the serial-to-parallel conversion circuit 11, converts the serial data into parallel data, and outputs the bits of the parallel data to the multipliers 13-1 to 13-m, respectively.
The shift register 12 receives a baseband signal from the left end, and shifts the received baseband signal bit by bit to the right. At this time, the bits in the shift register 12 are output to the multipliers 13-1 to 13-m, respectively.
The multipliers 13-1 to 13-m calculate bitwise products of the baseband signal output from the shift register 12 and the spreading code output from the serial-to-parallel conversion circuit 11, and output the obtained results to the adder 14.
The adder 14 calculates a sum of the outputs of the multipliers 13-1 to 13-m, and outputs the sum as a xe2x80x9ccorrelation output.xe2x80x9d The timing synchronization processing is performed under the condition that the spreading code output from the serial-to-parallel conversion circuit 11 is fixed, and received baseband signals are input in succession. Under this condition, a timing at which the correlation output is maximized is determined to be a synchronization timing.
However, in the above construction, it takes much time for the channelization-code generation circuit 10c to generate the hierarchized orthogonal code. The processing time can be reduced by arranging the circuit in a multiple form so that codes are generated in parallel.
FIG. 10 is a diagram illustrating an example of a multiple construction constituted by a plurality of hierarchical-orthogonal-code generation circuits. The example illustrated in FIG. 10 comprises a code-phase generation circuit 50, an increment circuit 51, AND gates 61 to 69, an EXCLUSIVE-OR gate 70, AND gates 71 to 79, an EXCLUSIVE-OR gate 80, and a register 81.
The code-phase generation circuit 50 generates and outputs 0, 2, . . . 510 (even numbers) as the code phase data.
The increment circuit 51 increments data output from the code-phase generation circuit 50, by one, and outputs the incremented data.
The AND gates 61 to 69 calculate and output bitwise logical products of the code phase data output from the code-phase generation circuit 50 and the hierarchical-orthogonal-code number k. At this time, the plurality of bits of the output of the code-phase generation circuit 50 supplied to the AND gates 61 to 69 are arranged in reverse order to the plurality of bits of the hierarchical-orthogonal-code number k supplied to the AND gates 61 to 69.
The AND gates 71 to 79 calculate and output bitwise logical products of the code phase data output from the increment circuit 51 and the hierarchical-orthogonal-code number k. At this time, the plurality of bits of the output of the increment circuit 51 supplied to the AND gates 71 to 79 are arranged in reverse order to the plurality of bits of the hierarchical-orthogonal-code number k supplied to the AND gates 71 to 79.
The phase data output from the code-phase generation circuit 50 are even numbers such as 0, 2, . . . 510, and the data output from the increment circuit 51 are odd numbers since the data output from the increment circuit 51 are generated by incrementing the data output from the code-phase generation circuit 50 by one. Therefore, the hierarchical-orthogonal-code generation circuit #1 generates a hierarchized orthogonal code having a code phase indicated by an even number, and the hierarchical-orthogonal-code generation circuit #2 generates a hierarchized orthogonal code having a code phase indicated by an odd number. In addition, since the hierarchical-orthogonal-code generation circuits #1 and #2 concurrently operate, the processing time required for code generation can be reduced to one-half the processing time in the construction of FIG. 9.
However, in the construction illustrated in FIG. 10, two hierarchical-orthogonal-code generation circuits #1 and #2 are necessary. Therefore, the hardware construction is complicated, and the complicated hardware increases the size of the circuit. Thus, the chip area also increases.
The present invention is made in view of the above problems, and the object of the present invention is to provide a code generation device which has a small chip size and can generate a code at high speed.
In order to accomplish the above object, a code generation device for generating a predetermined code is provided. The code generation device comprises: a binary-data generation circuit which generates every (m+1)th binary data item of successive binary numbers from 0 to n, where mxe2x89xa71 and nxe2x89xa72; a binary-data derivation circuit which derives m+1 binary data items indicating m+1 binary numbers from a binary number indicated by each of the binary data items which are generated by the binary-data generation circuit, where the m+1 binary numbers include the binary number indicated by the binary data item; a first processing circuit which performs a predetermined common operation on identical portions of the m+1 binary data items, where states of corresponding bits in the identical portions of the m+1 binary data items are identical; a second processing circuit which performs individually predetermined operations on non-identical portions of the m+1 binary data items, where states of corresponding bits in the non-identical portions of the m+1 binary data items are not identical; and a combining circuit which combines results of the operations by the first processing circuit and the second processing circuit.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiment of the present invention by way of example.